Chip design is divided into front-end design and back-end design. Front-end design (also known as logical design) and back-end design (back-end design (also known as physical design), and the design related to the process is back-end design.

Design schematic of the chip

Chip design before the end of the design

1. Specification formulation
Chip specifications, just like the function list, are the design requirements proposed by customers to the chip design company (called Fabless, the fabless design company), including the specific functional and performance requirements that the chip needs to achieve.

2. Detailed design

Fabless According to the specifications proposed by the customer, come up with the design solutions and specific implementation architecture, and divide the module functions.

3.HDL code

Use hardware description language (VHDL, Verilog HDL, industry companies generally use the latter) to describe the module function by code, that is, the actual hardware circuit function is described through HDL language to form RTL (register transfer level) code.

4. Simulation and verification

Simulation verification is to test the correctness of the coding design, and the inspection standard is the specification of the first step. To see if the design accurately meets all the requirements in the specification. Specifications are the gold standard for whether the design is correct or not. If all things violate and do not meet the specification requirements, you need to modify the design and coding. Design and simulation validation are iterative processes until the validation results show full compliance with the specification standards.

Simulations verify the VCS of the tool Synopsys, and also the Cadence's NC-Verilog.

5. Logical synthesis- -Design Compiler

Simulation verification passed, the logic synthesis. The result of logic synthesis is to translate the HDL code into gate level table netlist. Comprehensive needs to set constraints, is the integrated you want to synthesize the circuit in the area, timing and other target parameters to achieve the standard. Logic synthesis needs to be based on specific comprehensive libraries. In different libraries, the area and timing parameters of the basic standard unit (standard cell) of the gate circuit are different. Therefore, the selection of the comprehensive library is not the same, the comprehensive circuit in the timing, area is different. Generally speaking, after the completion of the synthesis, we need to do simulation verification again (this is also called post-simulation, before it is called pre-simulation).

The Design Compiler of the logic synthesis tool Synopsys.

6. STA

Static Timing Analysis (STA), static timing analysis, which also belongs to the category of verification, it is mainly timely used for verifying the circuit for the existence of establishment time (setup time) and holding time (hold time) violations (violation).